KetQat Decision Report -- Uncharacterised variational circuit

Executive summary

• Workload: Uncharacterised variational circuit. 80 logical qubits, 0 T gates and 0 Toffoli gates, depth 4000. Counts are USER_PROVIDED.
• No classical baseline was supplied, so no speedup or economic conclusion appears anywhere in this report.
• Conservative: INSUFFICIENT_EVIDENCE. unknown (Not computed: the factory could not be sized. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.) total, unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.) runtime, distance 23. Binding constraint: LOGICAL_QUBIT_CAPACITY.
• Base: INSUFFICIENT_EVIDENCE. unknown (Not computed: the factory could not be sized. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.) total, unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.) runtime, distance 11. Binding constraint: LOGICAL_QUBIT_CAPACITY.
• Optimistic: INSUFFICIENT_EVIDENCE. unknown (Not computed: the factory could not be sized. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.) total, unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.) runtime, distance 5. Binding constraint: LOGICAL_QUBIT_CAPACITY.

The decision, per assumption set

One row per assumption set. There is no aggregate row: the sets differ in what they assume, so a figure combining them would describe no machine anybody could build.

What would change this answer

• Synthesize the unsupported gates into Clifford+T and re-run the estimate.
• Lower the raw magic-state error, loosen the target state error, or select a distillation protocol that reaches the target.
• State the physical qubit capacity of the target device, with a source and a date.
• Measure the current classical solution on the real problem size and record the hardware and date.

Workload definition

• A circuit whose gates are neither Clifford nor T, submitted without synthesis, without a classical baseline and without a quantum cost model.
• Source: MANUAL_LOGICAL_COUNTS.
• Gate set: rx, ry, rz, cz.
• Logical qubits 80, depth 4000, 120000 gates, 0 Clifford, 0 T, 0 Toffoli, 120000 needing synthesis.
• Every gate is an arbitrary-angle rotation. Until they are synthesized into a Clifford+T basis there is no T count, and therefore no magic-state, factory or runtime figure to report.
• Reference case. Not evidence about any organisation's production workload.

Classical baseline

• None supplied.
• Resource estimation runs without one. Every economic and speedup conclusion is refused, by name, wherever it would otherwise appear.

Scenarios and assumptions

• Conservative (CONSERVATIVE, revision 1): Device parameters at the pessimistic end of what good superconducting hardware has demonstrated. Chosen so that a favourable answer here is not an artefact of favourable assumptions.
• Hardware: Generic reference device, conservative parameters, USER_ASSUMPTION, physical error rate 0.003, cycle 1000 ns, capacity unstated. A conventional pessimistic reading of demonstrated two-qubit error rates on superconducting devices, with the 1 microsecond surface-code cycle used throughout the fault-tolerance literature.
• QEC: SURFACE_CODE_ROTATED, threshold 0.01, prefactor 0.03 (Fowler conventional). Layout: LATTICE_SURGERY_2D.
• Factory: FIFTEEN_TO_ONE, raw state error 0.003, target 1e-10, 1 in parallel.
• Error budget 0.01. Runtime target none. Economic model: none supplied.
• Base (BASE, revision 1): The parameters most fault-tolerance resource analyses use: a 1e-3 physical error rate and a 1 microsecond surface-code cycle. Comparable with published estimates that state the same assumptions.
• Hardware: Generic reference device, standard literature parameters, USER_ASSUMPTION, physical error rate 0.001, cycle 1000 ns, capacity unstated. The physical error rate and cycle time used as the standard case in surface-code resource analyses, for example Gidney and Ekera (2019), arXiv:1905.09749.
• QEC: SURFACE_CODE_ROTATED, threshold 0.01, prefactor 0.03 (Fowler conventional). Layout: LATTICE_SURGERY_2D.
• Factory: FIFTEEN_TO_ONE, raw state error 0.001, target 1e-10, 1 in parallel.
• Error budget 0.01. Runtime target none. Economic model: none supplied.
• Optimistic (OPTIMISTIC, revision 1): Device parameters an order of magnitude better than the standard case, and a five-times faster cycle. This is a target, not an observation: it states what hardware would have to reach, which is the question the threshold engine answers rather than a prediction that it will.
• Hardware: Generic reference device, improvement-target parameters, USER_ASSUMPTION, physical error rate 0.0001, cycle 200 ns, capacity unstated. An improvement target stated for comparison, not a measurement or a vendor roadmap. No device is claimed to achieve these parameters.
• QEC: SURFACE_CODE_ROTATED, threshold 0.01, prefactor 0.03 (Fowler conventional). Layout: LATTICE_SURGERY_2D.
• Factory: FIFTEEN_TO_ONE, raw state error 0.0001, target 1e-10, 1 in parallel.
• Error budget 0.01. Runtime target none. Economic model: none supplied.

Resource estimates

• Conservative: feasible.
• Algorithm patches: 84,640 physical qubits (not the machine size).
• With routing space: 197,846 physical qubits.
• Magic-state factory: unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Total machine: unknown (Not computed: the factory could not be sized. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Code distance 23, unknown (120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.), 0 distillation level(s), unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Runtime unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.), limited by NOT_DETERMINED. Cycle-limited 0.092 s, factory-limited unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Achieved logical error 0.0051 probability against a budget of 0.01 probability.
• Arithmetic: Magic states: not computed. 120000 gate(s) that would contribute are neither Clifford nor T and have not been synthesized.
• Arithmetic: Logical cycles: max(depth 4000, 1) = 4000.
• Arithmetic: Occupied logical patches under LATTICE_SURGERY_2D: 187 (algorithm register 80).
• Arithmetic: Per-patch footprint: 2 x 23^2 = 1058 physical qubits.
• Arithmetic: Cycle-limited runtime: 4000 cycles x 23 rounds x 1000 ns = 9.200e-2 s.
• Warning: The magic-state demand is undetermined, not zero: every gate that would contribute to it is still un-synthesized. No factory footprint, no total machine size and no runtime are reported, because each would be a number invented to fill the gap.
• Base: feasible.
• Algorithm patches: 19,360 physical qubits (not the machine size).
• With routing space: 45,254 physical qubits.
• Magic-state factory: unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Total machine: unknown (Not computed: the factory could not be sized. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Code distance 11, unknown (120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.), 0 distillation level(s), unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Runtime unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.), limited by NOT_DETERMINED. Cycle-limited 0.044 s, factory-limited unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Achieved logical error 0.0096 probability against a budget of 0.01 probability.
• Arithmetic: Magic states: not computed. 120000 gate(s) that would contribute are neither Clifford nor T and have not been synthesized.
• Arithmetic: Logical cycles: max(depth 4000, 1) = 4000.
• Arithmetic: Occupied logical patches under LATTICE_SURGERY_2D: 187 (algorithm register 80).
• Arithmetic: Per-patch footprint: 2 x 11^2 = 242 physical qubits.
• Arithmetic: Cycle-limited runtime: 4000 cycles x 11 rounds x 1000 ns = 4.400e-2 s.
• Warning: The magic-state demand is undetermined, not zero: every gate that would contribute to it is still un-synthesized. No factory footprint, no total machine size and no runtime are reported, because each would be a number invented to fill the gap.
• Optimistic: feasible.
• Algorithm patches: 4,000 physical qubits (not the machine size).
• With routing space: 9,350 physical qubits.
• Magic-state factory: unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Total machine: unknown (Not computed: the factory could not be sized. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Code distance 5, unknown (120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.), 0 distillation level(s), unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Runtime unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.), limited by NOT_DETERMINED. Cycle-limited 0.004 s, factory-limited unknown (Not computed: 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Achieved logical error 0.0096 probability against a budget of 0.01 probability.
• Arithmetic: Magic states: not computed. 120000 gate(s) that would contribute are neither Clifford nor T and have not been synthesized.
• Arithmetic: Logical cycles: max(depth 4000, 1) = 4000.
• Arithmetic: Occupied logical patches under LATTICE_SURGERY_2D: 187 (algorithm register 80).
• Arithmetic: Per-patch footprint: 2 x 5^2 = 50 physical qubits.
• Arithmetic: Cycle-limited runtime: 4000 cycles x 5 rounds x 200 ns = 4.000e-3 s.
• Warning: The magic-state demand is undetermined, not zero: every gate that would contribute to it is still un-synthesized. No factory footprint, no total machine size and no runtime are reported, because each would be a number invented to fill the gap.

Sensitivity

• Conservative:
• PHYSICAL_ERROR_RATE = 7.50e-4: distance 11, unknown physical qubits
• PHYSICAL_ERROR_RATE = 1.50e-3: distance 15, unknown physical qubits
• PHYSICAL_ERROR_RATE = 3.00e-3: distance 23, unknown physical qubits
• PHYSICAL_ERROR_RATE = 6.00e-3: distance 53, unknown physical qubits
• PHYSICAL_ERROR_RATE = 1.20e-2: infeasible
• LOGICAL_ERROR_PREFACTOR = Fowler conventional: distance 23, unknown physical qubits
• LOGICAL_ERROR_PREFACTOR = Gidney-Fowler (Qualtran): distance 25, unknown physical qubits
• LAYOUT_MODEL = BARE_REGISTER: distance 23, unknown physical qubits
• LAYOUT_MODEL = LATTICE_SURGERY_2D: distance 23, unknown physical qubits
• CYCLE_TIME = 250 ns: distance 23, unknown physical qubits
• CYCLE_TIME = 500 ns: distance 23, unknown physical qubits
• CYCLE_TIME = 1000 ns: distance 23, unknown physical qubits
• CYCLE_TIME = 2000 ns: distance 23, unknown physical qubits
• CYCLE_TIME = 4000 ns: distance 23, unknown physical qubits
• ERROR_BUDGET = 1.00e-3: distance 27, unknown physical qubits
• ERROR_BUDGET = 1.00e-2: distance 23, unknown physical qubits
• ERROR_BUDGET = 1.00e-1: distance 19, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 3.00e-4: distance 23, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 3.00e-3: distance 23, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 3.00e-2: distance 23, unknown physical qubits
• Base:
• PHYSICAL_ERROR_RATE = 2.50e-4: distance 7, unknown physical qubits
• PHYSICAL_ERROR_RATE = 5.00e-4: distance 9, unknown physical qubits
• PHYSICAL_ERROR_RATE = 1.00e-3: distance 11, unknown physical qubits
• PHYSICAL_ERROR_RATE = 2.00e-3: distance 17, unknown physical qubits
• PHYSICAL_ERROR_RATE = 4.00e-3: distance 31, unknown physical qubits
• LOGICAL_ERROR_PREFACTOR = Fowler conventional: distance 11, unknown physical qubits
• LOGICAL_ERROR_PREFACTOR = Gidney-Fowler (Qualtran): distance 13, unknown physical qubits
• LAYOUT_MODEL = BARE_REGISTER: distance 11, unknown physical qubits
• LAYOUT_MODEL = LATTICE_SURGERY_2D: distance 11, unknown physical qubits
• CYCLE_TIME = 250 ns: distance 11, unknown physical qubits
• CYCLE_TIME = 500 ns: distance 11, unknown physical qubits
• CYCLE_TIME = 1000 ns: distance 11, unknown physical qubits
• CYCLE_TIME = 2000 ns: distance 11, unknown physical qubits
• CYCLE_TIME = 4000 ns: distance 11, unknown physical qubits
• ERROR_BUDGET = 1.00e-3: distance 13, unknown physical qubits
• ERROR_BUDGET = 1.00e-2: distance 11, unknown physical qubits
• ERROR_BUDGET = 1.00e-1: distance 9, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 1.00e-4: distance 11, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 1.00e-3: distance 11, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 1.00e-2: distance 11, unknown physical qubits
• Optimistic:
• PHYSICAL_ERROR_RATE = 2.50e-5: distance 5, unknown physical qubits
• PHYSICAL_ERROR_RATE = 5.00e-5: distance 5, unknown physical qubits
• PHYSICAL_ERROR_RATE = 1.00e-4: distance 5, unknown physical qubits
• PHYSICAL_ERROR_RATE = 2.00e-4: distance 7, unknown physical qubits
• PHYSICAL_ERROR_RATE = 4.00e-4: distance 9, unknown physical qubits
• LOGICAL_ERROR_PREFACTOR = Fowler conventional: distance 5, unknown physical qubits
• LOGICAL_ERROR_PREFACTOR = Gidney-Fowler (Qualtran): distance 7, unknown physical qubits
• LAYOUT_MODEL = BARE_REGISTER: distance 5, unknown physical qubits
• LAYOUT_MODEL = LATTICE_SURGERY_2D: distance 5, unknown physical qubits
• CYCLE_TIME = 50 ns: distance 5, unknown physical qubits
• CYCLE_TIME = 100 ns: distance 5, unknown physical qubits
• CYCLE_TIME = 200 ns: distance 5, unknown physical qubits
• CYCLE_TIME = 400 ns: distance 5, unknown physical qubits
• CYCLE_TIME = 800 ns: distance 5, unknown physical qubits
• ERROR_BUDGET = 1.00e-3: distance 7, unknown physical qubits
• ERROR_BUDGET = 1.00e-2: distance 5, unknown physical qubits
• ERROR_BUDGET = 1.00e-1: distance 5, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 1.00e-5: distance 5, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 1.00e-4: distance 5, unknown physical qubits
• RAW_MAGIC_STATE_ERROR = 1.00e-3: distance 5, unknown physical qubits

Advantage threshold conditions

• Conservative:
• The physical two-qubit error rate must stay below 8.73e-3 for any code distance to meet this error budget.
• Maximum physical error rate: at most 0.0087 probability.
• Required total capacity: unknown (The factory could not be sized, so no total is available. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Maximum cycle time to beat classical: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Maximum machine-second cost: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Break-even runtime: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Refused (NO_HARDWARE_CAPACITY): max_physical_error_rate_within_capacity -- No physical qubit capacity was stated for this hardware model, so there is nothing to fit within. A capacity was not assumed.
• Refused (NO_RUNTIME_TARGET): max_cycle_time_for_runtime_target -- This scenario states no runtime target, so there is no runtime to meet. A target was not assumed.
• Refused (NO_RUNTIME_TARGET): min_factory_throughput_for_runtime_target -- This scenario states no runtime target, so no throughput is required by one.
• Refused (FACTORY_NOT_SIZED): required_total_physical_qubit_capacity -- The factory could not be sized, so no total is available. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.
• Refused (NO_HARDWARE_CAPACITY): capacity_headroom -- No physical qubit capacity was stated for this hardware model.
• Refused (NO_CLASSICAL_BASELINE): max_cycle_time_to_beat_classical_runtime -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): runtime_speedup_over_classical -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): max_machine_cost_per_second -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): max_physical_qubit_second_cost -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): break_even_runtime -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): break_even_machine_cost_per_second -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): projected_quantum_cost -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): cost_ratio_to_classical -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Base:
• The physical two-qubit error rate must stay below 8.73e-3 for any code distance to meet this error budget.
• Maximum physical error rate: at most 0.0087 probability.
• Required total capacity: unknown (The factory could not be sized, so no total is available. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Maximum cycle time to beat classical: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Maximum machine-second cost: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Break-even runtime: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Refused (NO_HARDWARE_CAPACITY): max_physical_error_rate_within_capacity -- No physical qubit capacity was stated for this hardware model, so there is nothing to fit within. A capacity was not assumed.
• Refused (NO_RUNTIME_TARGET): max_cycle_time_for_runtime_target -- This scenario states no runtime target, so there is no runtime to meet. A target was not assumed.
• Refused (NO_RUNTIME_TARGET): min_factory_throughput_for_runtime_target -- This scenario states no runtime target, so no throughput is required by one.
• Refused (FACTORY_NOT_SIZED): required_total_physical_qubit_capacity -- The factory could not be sized, so no total is available. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.
• Refused (NO_HARDWARE_CAPACITY): capacity_headroom -- No physical qubit capacity was stated for this hardware model.
• Refused (NO_CLASSICAL_BASELINE): max_cycle_time_to_beat_classical_runtime -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): runtime_speedup_over_classical -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): max_machine_cost_per_second -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): max_physical_qubit_second_cost -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): break_even_runtime -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): break_even_machine_cost_per_second -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): projected_quantum_cost -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): cost_ratio_to_classical -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Optimistic:
• The physical two-qubit error rate must stay below 8.73e-3 for any code distance to meet this error budget.
• Maximum physical error rate: at most 0.0087 probability.
• Required total capacity: unknown (The factory could not be sized, so no total is available. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.).
• Maximum cycle time to beat classical: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Maximum machine-second cost: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Break-even runtime: unknown (Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.).
• Refused (NO_HARDWARE_CAPACITY): max_physical_error_rate_within_capacity -- No physical qubit capacity was stated for this hardware model, so there is nothing to fit within. A capacity was not assumed.
• Refused (NO_RUNTIME_TARGET): max_cycle_time_for_runtime_target -- This scenario states no runtime target, so there is no runtime to meet. A target was not assumed.
• Refused (NO_RUNTIME_TARGET): min_factory_throughput_for_runtime_target -- This scenario states no runtime target, so no throughput is required by one.
• Refused (FACTORY_NOT_SIZED): required_total_physical_qubit_capacity -- The factory could not be sized, so no total is available. 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the magic-state demand is undetermined rather than zero. No factory can be sized, and no total machine size follows, until those gates are synthesized into a Clifford+T basis.
• Refused (NO_HARDWARE_CAPACITY): capacity_headroom -- No physical qubit capacity was stated for this hardware model.
• Refused (NO_CLASSICAL_BASELINE): max_cycle_time_to_beat_classical_runtime -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): runtime_speedup_over_classical -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): max_machine_cost_per_second -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): max_physical_qubit_second_cost -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): break_even_runtime -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): break_even_machine_cost_per_second -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): projected_quantum_cost -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.
• Refused (NO_CLASSICAL_BASELINE): cost_ratio_to_classical -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than. No baseline was assumed.

Decision assessment

• Conservative: INSUFFICIENT_EVIDENCE
• The computation cannot be assessed under this model because a required component could not be computed. The magic-state factory could not be sized, so no total machine size exists. The algorithm footprint is reported as a component of the requirement, never as the requirement. The binding constraint is logical-qubit capacity: the algorithm register and its routing space occupy 187 logical patches, which dominate the footprint.
• SCIENTIFIC_FEASIBILITY: INSUFFICIENT_EVIDENCE -- 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the fault-tolerant cost cannot be determined at all until those gates are synthesized into a Clifford+T basis.
• ENGINEERING_FEASIBILITY: INSUFFICIENT_EVIDENCE -- The magic-state factory could not be sized, so no total machine size exists. The algorithm footprint is reported as a component of the requirement, never as the requirement.
• HARDWARE_READINESS: INSUFFICIENT_EVIDENCE -- No physical qubit capacity is stated for this hardware model, so there is nothing to compare the requirement against. A capacity was not assumed. The device parameters are an assumption, not an observation of a working machine, so this reading is conditional on them being reached.
• ECONOMIC_READINESS: INSUFFICIENT_EVIDENCE -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than.
• EVIDENCE_CONFIDENCE: NOT_SATISFIED -- Logical counts are USER_PROVIDED; hardware parameters are USER_ASSUMPTION at MEDIUM confidence; the classical baseline is absent; the quantum cost model is absent. These are different kinds of claim and are not averaged into a score.
• SENSITIVITY_RISK: INSUFFICIENT_EVIDENCE -- No sensitivity spread could be computed, because the estimate produced no total machine size to vary.
• Reason codes: DISTILLATION_TARGET_UNREACHED, FACTORY_NOT_SIZED, HARDWARE_BASIS_USER_ASSUMPTION, NO_CLASSICAL_BASELINE, NO_STATED_CAPACITY, T_COUNT_NOT_DETERMINED, UNSUPPORTED_GATES_PRESENT, WORKLOAD_COUNTS_USER_PROVIDED.
• Next: Synthesize the unsupported gates into Clifford+T and re-run the estimate.
• Next: Lower the raw magic-state error, loosen the target state error, or select a distillation protocol that reaches the target.
• Next: State the physical qubit capacity of the target device, with a source and a date.
• Next: Measure the current classical solution on the real problem size and record the hardware and date.
• Base: INSUFFICIENT_EVIDENCE
• The computation cannot be assessed under this model because a required component could not be computed. The magic-state factory could not be sized, so no total machine size exists. The algorithm footprint is reported as a component of the requirement, never as the requirement. The binding constraint is logical-qubit capacity: the algorithm register and its routing space occupy 187 logical patches, which dominate the footprint.
• SCIENTIFIC_FEASIBILITY: INSUFFICIENT_EVIDENCE -- 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the fault-tolerant cost cannot be determined at all until those gates are synthesized into a Clifford+T basis.
• ENGINEERING_FEASIBILITY: INSUFFICIENT_EVIDENCE -- The magic-state factory could not be sized, so no total machine size exists. The algorithm footprint is reported as a component of the requirement, never as the requirement.
• HARDWARE_READINESS: INSUFFICIENT_EVIDENCE -- No physical qubit capacity is stated for this hardware model, so there is nothing to compare the requirement against. A capacity was not assumed. The device parameters are an assumption, not an observation of a working machine, so this reading is conditional on them being reached.
• ECONOMIC_READINESS: INSUFFICIENT_EVIDENCE -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than.
• EVIDENCE_CONFIDENCE: NOT_SATISFIED -- Logical counts are USER_PROVIDED; hardware parameters are USER_ASSUMPTION at MEDIUM confidence; the classical baseline is absent; the quantum cost model is absent. These are different kinds of claim and are not averaged into a score.
• SENSITIVITY_RISK: INSUFFICIENT_EVIDENCE -- No sensitivity spread could be computed, because the estimate produced no total machine size to vary.
• Reason codes: DISTILLATION_TARGET_UNREACHED, FACTORY_NOT_SIZED, HARDWARE_BASIS_USER_ASSUMPTION, NO_CLASSICAL_BASELINE, NO_STATED_CAPACITY, T_COUNT_NOT_DETERMINED, UNSUPPORTED_GATES_PRESENT, WORKLOAD_COUNTS_USER_PROVIDED.
• Next: Synthesize the unsupported gates into Clifford+T and re-run the estimate.
• Next: Lower the raw magic-state error, loosen the target state error, or select a distillation protocol that reaches the target.
• Next: State the physical qubit capacity of the target device, with a source and a date.
• Next: Measure the current classical solution on the real problem size and record the hardware and date.
• Optimistic: INSUFFICIENT_EVIDENCE
• The computation cannot be assessed under this model because a required component could not be computed. The magic-state factory could not be sized, so no total machine size exists. The algorithm footprint is reported as a component of the requirement, never as the requirement. The binding constraint is logical-qubit capacity: the algorithm register and its routing space occupy 187 logical patches, which dominate the footprint.
• SCIENTIFIC_FEASIBILITY: INSUFFICIENT_EVIDENCE -- 120000 gate(s) are neither Clifford nor T and the circuit records no T or Toffoli gates, so the fault-tolerant cost cannot be determined at all until those gates are synthesized into a Clifford+T basis.
• ENGINEERING_FEASIBILITY: INSUFFICIENT_EVIDENCE -- The magic-state factory could not be sized, so no total machine size exists. The algorithm footprint is reported as a component of the requirement, never as the requirement.
• HARDWARE_READINESS: INSUFFICIENT_EVIDENCE -- No physical qubit capacity is stated for this hardware model, so there is nothing to compare the requirement against. A capacity was not assumed. The device parameters are an assumption, not an observation of a working machine, so this reading is conditional on them being reached.
• ECONOMIC_READINESS: INSUFFICIENT_EVIDENCE -- Insufficient evidence for economic comparison: no classical baseline was supplied, so there is nothing to be faster or cheaper than.
• EVIDENCE_CONFIDENCE: NOT_SATISFIED -- Logical counts are USER_PROVIDED; hardware parameters are USER_ASSUMPTION at LOW confidence; the classical baseline is absent; the quantum cost model is absent. These are different kinds of claim and are not averaged into a score.
• SENSITIVITY_RISK: INSUFFICIENT_EVIDENCE -- No sensitivity spread could be computed, because the estimate produced no total machine size to vary.
• Reason codes: DISTILLATION_TARGET_UNREACHED, FACTORY_NOT_SIZED, HARDWARE_BASIS_USER_ASSUMPTION, HARDWARE_CONFIDENCE_LOW, NO_CLASSICAL_BASELINE, NO_STATED_CAPACITY, T_COUNT_NOT_DETERMINED, UNSUPPORTED_GATES_PRESENT, WORKLOAD_COUNTS_USER_PROVIDED.
• Next: Synthesize the unsupported gates into Clifford+T and re-run the estimate.
• Next: Lower the raw magic-state error, loosen the target state error, or select a distillation protocol that reaches the target.
• Next: State the physical qubit capacity of the target device, with a source and a date.
• Next: Measure the current classical solution on the real problem size and record the hardware and date.

Scenario comparison

• No aggregate row is produced. Scenarios differ in their assumptions, and a mean of results computed under different assumptions is a number none of the models predicts, carrying the apparent authority of all of them. Each row is read on its own terms.
• Conservative: INSUFFICIENT_EVIDENCE, unknown physical qubits, unknown, distance 23, factory share unknown, economic INSUFFICIENT_EVIDENCE, evidence LOW.
• Base: INSUFFICIENT_EVIDENCE, unknown physical qubits, unknown, distance 11, factory share unknown, economic INSUFFICIENT_EVIDENCE, evidence LOW.
• Optimistic: INSUFFICIENT_EVIDENCE, unknown physical qubits, unknown, distance 5, factory share unknown, economic INSUFFICIENT_EVIDENCE, evidence LOW.

Missing evidence

• A Clifford+T synthesis of the non-Clifford, non-T gates in this circuit. Without it the T count, and therefore every magic-state and factory figure, is not merely approximate but absent.
• A distillation configuration that reaches the target magic-state error. Until one exists the factory footprint, and therefore the machine size, is not computed.
• The physical qubit capacity of the device under consideration. Without it, 'does it fit' has no answer.
• A dated observation of a real device meeting these physical error rate and cycle time parameters.
• A classical baseline: runtime, cost, hardware, problem size, solution quality, and the date it was measured.

Limitations

• Resource estimates are modelled, not measured. No device was run.
• The logical-error prefactor is fitted and its provenance is weak; the alternative published value is reported as model sensitivity on every estimate.
• The magic-state factory footprint and throughput are models of the standard construction, not published or measured figures.
• The error budget is allocated across the algorithm's own logical qubits; routing patches are charged for space but not against the budget.
• One QEC scheme is modelled. Other codes, other layouts, and other hardware modalities are out of scope here.
• Nothing in this bundle predicts when any device will meet any condition it states.
• No classical baseline was supplied, so no economic or speedup conclusion is drawn anywhere in this bundle.

Sources

• Surface-code threshold and logical-error model: Fowler, Mariantoni, Martinis, Cleland -- Surface codes: Towards practical large-scale quantum computation Published 2012-08-04. Retrieved 2026-08-13.
  HIGH